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INDEX PRELIMINARY
MX98746
100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER
1.0 FEATURES
* IEEE 802.3u D5 repeater and management compatible * Support 5 TX/FX ports * Support 8-scale utilization and collision rate LED display * Asynchronous Expansion port clock supported for easily stackable application * Separate jabber and partition state machines for each port * On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source * Contents of internal register loaded from EEPROM * CMOS device features high integration and low power with a signle +5V supply * 128-PIN PQFP
2.0 GENERAL DESCRIPTION
The MX98746, Second generation 100 Mb/s TX/FX Hub Controller, is designed specifically to meet the needs of today's high speed Fast Ethernet networking systems. The MX98746 is fully IEEE 802.3u D5 clause 27 repeater compatible. Difference from MX98741 and MX98745, MX98746 support 5 dedicated TX/FX ports. All contents of internal registers are loaded from EEPROM in MX98746. If system application prefers default setting instead of using contents from EEPROM, EEPROM operation can be disabled by setting EECONF to low. This feature faciliates system modulization application. 8 scale of utilization and collision rate LED are also provided by MX98746. They are 1%, 3%, 5%, 10%, 20%, 40%, 60% and 80+% for network utilization, and 1%, 3%, 5%, 8%, 10%, 13%, 15% and 20+% for collision rate. The defination for utiliztion is Mbs Received/100 Mb within one second sampling period. Meanwhile, RX/ LINK, Partition, Isolation and Collision status are also provided through LED display. A great improvement in MX98746 (compared to MX98741) is that it also provides "asynchronous expansion port data transfer mode" to make stackable design more easier.
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MX98746
3.0 BLOCK DIAGRAMS
MDC
MDIO LSCLK SIGDET[4:0]
Jabber Clock Generator RESEL Port 0 5B RX/ Port 0 4B RX SCRCTRL Reperater Core & Comtrol/Status Registers Port 0 5B TX Relative Function TDAT0[4:0] RDAT0[4:0] RSCLK0
Port 4 RX Relative Function Port 4 TX Relative Function
RDAT4[4:0] RSCLK4
TDAT4[4:0]
Expansion Port Function
Utilization/ Status LED Display Function
EDACT JAMI EDAT[4:0] EPCLK JAMO EDENL EDCRS ANYACT LED[7:0] LDSEL[2:0]
Figure 3-1 Block Diagram for MX98746
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RSCLK4
SIGDET4
RDAT44
RDAT43
RDAT42
RDAT41
RDAT40
TDAT44
TDAT43
TDAT42
TDAT41
TDAT40
GND VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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128
102 VDD GND TDAT34 TDAT33 TDAT32 TDAT31 TDAT30 VDD RDAT34 RDAT33 RDAT32 RDAT31 RDAT30 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GND SIGDET3 RSCLK3 VDD TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 GND RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 SIGDET2 RSCLK2 LED7/PHY4 LED6/PHY3 LED5/PHY2 LED4/PHY1 LED3/PHY0 LED2 LED1 GND 101 100 99 98 97 96 95 94 93 92 91 90
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
GND RSCLK0 SIGDET0 RDAT00 RDAT01 RDAT02 RDAT03 RDAT04 TDAT00 TDAT01 TDAT02 TDAT03 TDAT04 GND RSCLK1 SIGDET1 GND RDAT10 RDAT11 RDAT12 RDAT13 RDAT14 VDD TDAT10 TDAT11 TDAT12 TDAT13 TDAT14 VDD LSCLK TSEL TEST XCOLED SCRCTRL RESETL MIDC MDIO VDD 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
4.0 PIN CONFIGURATION
1
MX98746
3
39 VDD 40 GND 41 GND 42 GND 43 EDAT0 44 EDAT1 45 EDAT2 46 EDAT3 47 EDAT4 48 EPCLK 49 JAMO 50 JAMI 51 EDCRS 52 EDENL 53 GND 54 ANYACT 55 EDACT 56 EECS 57 VDD
58 LEDEN
59 LSD0/EECONF
60 LDS1/EDI
61 GND
62 LDS2/EDO
63
64 VDD
MX98746
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INDEX
INDEX
MX98746
5.0 PIN DESCRIPTION
Table 5-1 Pin Description for MX98746 A. MX Data Transceiver Interface (MX98704 or MX98705), 61 pins Name I/O Description TDAT[0:4][0:4] O, Transmit Data. These five outputs are 5B encoded transmit data TTL symbols, driven at the rising edge of LSCLK. TDAT4 is the Most Significant Bit.
PAD # 9-13 24-28 81-85 96-100 116-120 30
LSCLK
I, TTL I, TTL
4-8 18-22 75-79 90-94 111-115 2 15 73 87 108 3 16 74 88 109 49
RDAT[0:4][0:4]
Local Synchrnous Clock. This pin supplies the frequency reference to the MX98745 within same HUB. It should be driven by a crystal-controlled 25M clock source. Receive Data. These 5 bit parallel data symbol from transceiver are latched by the rising edge of RSCLK of each port. RDAT4 is the Most Significant Bit.
RSCLK[0:4]
I, TTL
Recovered Symbol Clock. This is a 25 MHz clock, which is derived from the clock synchroniztion PLL circuit.
SIGDET[0:4]
I, TTL
Signal Detect. This signal indicates that the received signal is above the detection threshold and will be used for the link test state machine.
JAMO
50
JAMI
B. Expansion Port, 12 pins O, Forced Jam Out. Active High. The OR'd forced jam signals controlled CMOS by Carrier Integrity Monitor of each port. If collision occurs inside the XRC II (exclude JAMI), this pin is also asserted. I, TTL Forced Jam Input. Active High. Asserted by external arbitor, and XRCII will generate JAM patterns to all its ports whenever this signal is validate more than 40 ns. This signal is filtered by LSCLK for 40ns internally.
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MX98746
PAD # 52 Name EDENL I/O Description I, Sche Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC II will not drive data onto EDAT until this pin is asserted. Assertion time less than 40ns will not be recognized by XRC II. I/O, Expansion Data. Bidirectional 5 bit-wide data. By default, EDAT is an TTL input. An external arbitor coordinates multiple devices on EDAT. I/O, Expansion port Data Clock. This clock will be outputed by XRCII along TTL with the EDAT[0:4]. Another module of XRCII should use this signal as expansion port data input clock. O, Any Activity. Active High. When XRCII tries to release data onto EDAT, CMOS this pin will be asserted by XRC II. I, Sche Expansion Data Carrier Sense. When this pin is asserted, XRC II will recognize that there is activity on expansion port data bus EDAT and perform corresponding activity within XRCII itself. O, Expansion Data Activity. When XRCII detects that EDENL is asserted CMOS by external arbitor, it will assert EDACT high. System application can use this signal to control the data bus flow of EDAT. C. Management, 2 pins I,TTL Management Data Clock. The timing reference for MDIO. The minumum high and times are 200 ns each. I/O, Management Data Input/Output. A bi-directional signal. The selection of input/output direction is based on IEEE802.3u management functions (Section 22.2.4). D. Test/Miscellaneous, 5 pins I Test. Industrial test pin. Set to 0 for normal operation. When programmed to logic 1, XRC II is in test mode. I Test Select. Used by industrial test. Internal Pull down. Set to 0 for normal operatioon. O, LED I,TTL Collision LED. Active low. When there is collision within the XRC II, XCOLED will be on for 80ms and off for 20ms. Scrambler Control. Active High. When this pin is set to 0, All TX port will be set to descramble mode, i.e. contents of register #17 will be disabled. When this pin is set to 1, Each port's scrambler/descrambler is controller by corresponding bit in register #17. Internally pullup. I, Sche Reset. Active Low. Will be filtered by LSCLK within the MX98746.
43-47 48
EDAT[0:4] EPCLK
54 51
ANYACT EDCRS
55
EDACT
36 37
MDC MDIO TTL
32 31 33 34
TEST TSEL XCOLED SCRCTRL
35
RESETL
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MX98746
E. LED Display/EEPROM Interface, 13 pins I/O Description O, LED Output Enable. When LEDEN is asserted high, it means that CMOS varuous internal status is shown on LED[7:0] according to the value on LDS[2:0] I/O, LED Output Select. LDS0 is internally pulldown and value on LDS0 will TTL be latched internally by MX98746 at the rising edge of RESETL as the value of EECONF. Value on LDS1 will act as EEPROM Data Input signal during EEPROM loading operation (after power on reset and EECONF is set to 1) and LDS2 will be data output from EEPROM. When EECONF is low, EEPROM operation will be disabled. After power on reset, LDS[2:0] work as the select pins of LED[7:0] output. The following are corresponding definition LDS2 LDS1 LDS0 0 0 1 Link/Receive 0 1 0 Isolation 0 1 1 Partition 1 0 0 Utilization 1 0 1 Collision Rate I/O, LED0/EPROM Clock/Partition Select. value on this pin will be latched TTL by MX98746 at the rising edge of RESET as the value of Partition Select (PARSEL). When EECONF is set to 1, this pin will work as EEPROM clock pin and output by MX98746 after power on reset. When EEPROM operation is enabled, internal repeater function will be disable until contents in EEPROM is loaded into MX98746. After EEPROM operation is completed, this pin will indicate 1% Network utilization and 1% collision rate according to the value on LDS[2:0]. 66 LED1 I/O, TTL I/O, TTL LED1. In normal operation (after power on reset), this pin will display port 2's Receive/Link, Partition, Isolation status and indicates 3% Net work utilization and 3% collision rate according to the value on LDS[2:0]. LED2. In normal operation (after power on reset), this pin will display port 3's Receive/Link, Partition, Isolation status and indicates 5% Net work utilization and 5% collision rate according to the value on LDS[2:0].
PAD # 58
Name LEDEN
62, 60, 59
LDS2/EDO, LDS1/EDI, LDS0/EECONF
63
LED0/EECK/ PARSEL
66
LED2
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MX98746
F. LED Display (Continued) LED 3/Physical Address 0. Value on LED3 will be latched at the rising edge of RESET as the setting of Device physical address 0. If EECONF is set to 1, PHY0 will be overwritten by the contents of EEPROM. After EEPROM operation is completed (in case EECONF is set to 1), this pin will indicate 10% Network utilization and 8% collision rate according to the value on LDS[2:0] LED 4/Physical Address 1. Value on LED4 will be latched at the rising edge of RESETL as the physical address 1 of MX98746. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 4's Receivee/Link, Partition, Isolation status and indicates 20% Network utilization and 10% collision rate according to the value on LDS[2:0]. LED 5/Physical Address 2. Value on LED5 will be latched at the rising edge of RESETL as the physical address 2 of MX98746. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will indicate 40% Network utilization and 13% collision rate according to the value on LDS[2:0].
68
LED3/ PHY0
I/O, TTL
69
LED4/ PHY1
I/O, TTL
70
LED5/ PHY2
I/O, TTL
F. LED Display (Continued)
PAD # 71 Name LED6/ PHY3 I/O I/O, TTL Description LED 6/Physical Address 3. Value on LED6 will be latched at the rising edge of RESETL as the physical address 3 of MX98746. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 0's Receivee/Link, Partition, Isolation status and indicates 60% Network utilization and 15% collision rate according to the value on LDS[2:0]. LED 7/Physical Address 4. Value on LED7 will be latched at the rising edge of RESETL as the physical address 4 of MX98746. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 1's Receivee/Link, Partition, Isolation status and indicates 80+% Network utilization and 20+% collision rate according to the value on LDS[2:0].
72
LED7/ PHY4
I/O, TTL
56
EECS
O, EEPROM Chip Select. Output by MX98746 when EECONF is set and CMOS EEPROM operation is activated by MX98746.
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MX98746
G. Power/Ground Pins Description
PAD # 1,14,17, 40, 41, 42, 53, 61, 65, 80, 89, 101,103, 104, 105, 106, 107, 121, 122, 123, 124, 125, 126, 127, 128 23, 29, 38, 39, 57, 64, 86, 95, 102, 110
Name
I/O
GND
Ground.
VDD
5V Power Supply.
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MX98746
6.0 FUNCTIONAL AND OPERATION DESCRIPTION
6.1 All TX MODE SELECTED
EEPROM
XRC
Arbitor
XRC
DT & PMD Port 0
DT& PMD Port 4
DT& PMD Port 5
DT& PMD Port 9
Figure 6-1 Pure TX Mode operation for MX98746
6.2 TX AND FX MIXED MODE
EEPROM
Arbitor
XRC
XRC
FX Port 0 Port 0
DT& PMD Port 4
DT& PMD Port 5
DT& PMD Port 9
Figure 6-2 TX/FX Mixed Mode operation for MX98746
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MX98746
6.3 INTERNAL REGISTERS All the registers can be accessed through MII's MDC and MDIO. Although XRC II connects to multiple 100TX PHY's, they are all identical. Each XRC has only one PHY address as defined by PHY[4:0] pins (which will be latched by the rising edge of RESETL, and will be overwritten by the contents of EEPROM whenever EECONF is set to 1). If multiple XRC's are on the same MDIO bus, each of them should have different PHY address. Other non-XRC PHY devices (e.g. T4) are also allowed to be managed with the same management interface as long as PHY address of each device is distinct. Register 0 and 1 are Command and Status registers which specified in [1]. Additional registers provided by MX98746 is located from address 16 to 31 (decimal value). Port Control Registers are located from address #16 to address #20. These control registers include port reset control register (#16), Port Scremabler control register (#17), Port Enable Control Register (#18), Isolation Disable Control Register (#19) and Partition Disable Control Register (#20). Port Status Registers are located from address #25 to address #29. These registers include Link Status Register (#25), Partition Status Register (#26), Elastic Buffer Status Register (#27), Jabber Status Register (#28) and Isolation Status Register (#29). Register #31 is Configuration Register. Value latched at the rising edge of RESETL will be stored in this register. Value on this register will be overwritten by contents of EEPROM in case EECONF is set to 1.
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MX98746
A. Command Register (register #0) (R/W) Table 6-1 Control Register Bit Definition Bit(s) Name 0.15 Reset
0.14
Loop Back
0.13 0.12
Speed Selection Auto-Negotiation Enable
0.11
Power Down
0.10 0.9
Isolate Restart
0.8 0.7
Duplex Mode Collision Test
0.6:0
Reserved
Description 1 : PHY reset. A 240ns reset pulse will be generated to reset XRC internal logic. 0 : normal operation. 1 : enable loopback mode. 0 : disable loopback mode. The default setting is 0. Forced to 1 and indicate 100 Mb/s. Write 0 to this bit has no effect. Forced to 0 and indicate that Auto-Negotiation process is disable. Write 1 to this bit has no effect. 1 : power down. COCLK and TXCLK for each port will be disabled. Clock for Management Block will keep running. During Power down, all state machines will be reset to its default state. 0 : normal operation. 1 : electrically Isolate PHY from MII 0 : normal operation Auto-Negotiation Forced to 0 and indicate that Auto-Negotiation process is disable. Write 1 to this bit has no effect. Forced to 0 and indicate that only Half Duplex is available. Write 1 to this bit has no effect. 1 : enable COL signal test. The PHY will assert the COL signal within 5120 ns in response to the assertion of TXEN. While this bit is set to one, the PHY will deassert the COL signal within 40 ns in response to the deassertion of TXEN. 0 : normal operation. Set to 0 after power on reset. Value 0 will be read when one tries to read these bits.
R/W R/W SC R/W
R R
R/W
R/W R
R R/W
R
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MX98746
B. Status Register (register #1) (R) Table 6-2 Status Register Bit Definition Bit(s) Name 1.15 100BASE-T4 1.14 1.13 1.12 1.11 1.10:6 1.5 1.4 1.3 1.2 1.1 1.0 100BASE-X Full Duplex 100BASE-X Half Duplex 10 Mb/s Full Duplex 10 Mb/s Half Duplex Reserved Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability
Description Forced to 0 and indicates that XRC is not able to perform 100BASE-T4. Forced to 0 and indicates that XRC is not able to perform 100BASE-X Fill Duplex. Forced to 1 and indicates that XRC is able to perform 100BASE-X Half Duplex. Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Full Duplex. Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Half Duplex. Value 0 will be released by XRC when read. Forced to 0. Forced to 0. Forced to 0. 1 : All ports are link up. 0 : Any port is link fail. Will be set to 1 after this port is read. 1 : Jabber condition in any port is detected. 0 : No Jabber condition detected for all ports Forced to 1.
R/W R R R R R R R R R R R R
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MX98746
C. Port Reset Register (register #16) (R/W) Table 6-3 Port Reset Register Bit Definition Bit(s) Name Description 16.15:8 Reserved Ignored when read. 16.7 ResetP1 1 : reset Port 1's Logic. 0 : not reset Port 1's Logic. Power on low. 16.6 ResetP0 1 : reset Port 0's Logic. 0 : not reset Port 0's Logic. Power on low. 16.5 Reserved Ignored when read 16.4 ResetP4 1 : reset Port 4's Logic. 0 : not reset Port 4's Logic. Power on low. 16.3 Reserved Ignored when read 16.2 ResetP3 1 : reset Port 3's Logic. 0 : not reset Port 3's Logic. Power on low. 16.1 ResetP2 1 : reset Port 2's Logic. 0 : not reset Port 2's Logic. Power on low. 16.0 Reserved Ignored when read
R/W R R/W
R/W
R R/W
R R/W
R/W
R
Each bit will not clear to 0 automatically whenever it is set to 1. To ensure the MX98746 works properly, one should write 0 back to Port reset register after written 1 to corresponding bit.
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MX98746
D. Scrambler Control Register (register #17) (R/W) Table 6-4 Scrambler Control Register Bit Definition Bit(s) Name Description 17.15:8 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 17.7 ScrenP1 1 : Enable Scrambler/Descrambler at Port 1 0 : Disable Scrambler/Descrambler at Port 1 The default value after power on is 1. 17.6 ScrenP0 1 : Enable Scrambler/Descrambler at Port 0 0 : Disable Scrambler/Descrambler at Port 0 The default value after power on is 1. 17.5 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 17.4 ScrenP4 1 : Enable Scrambler/Descrambler at Port 4 0 : Disable Scrambler/Descrambler at Port 4 The default value after power on is 1. 17.3 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 17.2 ScrenP3 1 : Enable Scrambler/Descrambler at Port 3 0 : Disable Scrambler/Descrambler at Port 3 The default value after power on is 1. 17.1 ScrenP2 1 : Enable Scrambler/Descrambler at Port 2 0 : Disable Scrambler/Descrambler at Port 2 The default value after power on is 1. 17.0 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued Note : When SCRCTRL is set to 0, contents of this register will be disabled.
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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MX98746
E. Port Enable Control Register (register #18) (R/W) (Continued) Table 6-5 Port Enable Control Register Bit Definition Bit(s) Name Description 18.15:8 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 18.7 EnP1 1 : Enable RX/TX functions at Port 1. 0 : Disable RX/TX functions at Port 1. The default value after power on is 1. 18.6 EnP0 1 : Enable RX/TX functions at Port 0. 0 : Disable RX/TX functions at Port 0. The default value after power on is 1. 18.5 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 18.4 EnP4 1 : Enable RX/TX functions at Port 4. 0 : Disable RX/TX functions at Port 4. The default value after power on is 1. 18.3 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 18.2 EnP3 1 : Enable RX/TX functions at Port 3. 0 : Disable RX/TX functions at Port 3. The default value after power on is 1. 18.1 EnP2 1 : Enable RX/TX functions at Port 2. 0 : Disable RX/TX functions at Port 2. The default value after power on is 1. 18.0 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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MX98746
F. Isolation Disable Register (register #19) (R/W) Table 6-6 Isolation Disable Register Bit Definition Bit(s) Name Description 19.15:8 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 19.7 ISODIS1 1 : Port 1 Isolation function is disabled 0 : Port 1 Isolation function is not disabled. The default value is 0 after reset. 19.6 ISODIS0 1 : Port 0 Isolation function is disabled 0 : Port 0 Isolation function is not disabled. The default value is 0 after reset. 19.5 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 19.4 ISODIS4 1 : Port 4 Isolation function is disabled 0 : Port 4 Isolation function is not disabled. The default value is 0 after reset. 19.3 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 19.2 ISODIS3 1 : Port 3 Isolation function is disabled 0 : Port 3 Isolation function is not disabled. The default value is 0 after reset. 19.1 ISODIS2 1 : Port 2 Isolation function is disabled 0 : Port 2 Isolation function is not disabled. The default value is 0 after reset. 19.0 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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MX98746
G. Partition Disable Register (register #20) (R/W) Table 6-7 Partition Disable Register Bit Definition (Continued) Bit(s) Name Description 20.15:8 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 20.7 PTNDIS1 1 : Port 1 Parition function is disbled. 0 : Port 1 Partition function is not disabled. The default value is 0 after reset. 20.6 PTNDIS0 1 : Port 0 Parition function is disbled. 0 : Port 0 Partition function is not disabled. The default value is 0 after reset. 20.5 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 20.4 PTNDIS4 1 : Port 4 Parition function is disbled. 0 : Port 4 Partition function is not disabled. The default value is 0 after reset. 20.3 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 20.2 PTNDIS3 1 : Port 3 Parition function is disbled. 0 : Port 3 Partition function is not disabled. The default value is 0 after reset. 20.1 PTNDIS2 1 : Port 2 Parition function is disbled. 0 : Port 2 Partition function is not disabled. The default value is 0 after reset. 20.0 Reserved Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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MX98746
H. Link Status Register (register #25) (R) Table 6-8 Link Status Register Bit Definition Bit(s) Name Description 25.15:8 Reserved Always 0. 25.7 LinkP1 1 : Link Status is OK at port 1 0 : Link Status is Fail at Port 1 Status is updated at every LSCLK clock. 25.6 LinkP0 1 : Link Status is OK at port 0 0 : Link Status is Fail at Port 0 Status is updated at every LSCLK clock. 25.5 Reserved Ignored when read 25.4 LinkP4 1 : Link Status is OK at port 4 0 : Link Status is Fail at Port 4 Status is updated at every LSCLK clock. 25.3 Reserved Ignored when read 25.2 LinkP3 1 : Link Status is OK at port 3 0 : Link Status is Fail at Port 3 Status is updated at every LSCLK clock. 25.1 LinkP2 1 : Link Status is OK at port 2 0 : Link Status is Fail at Port 2 Status is updated at every LSCLK clock. 25.0 Reserved Ignored when read
R/W R R
R
R R
R R
R
R
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MX98746
I. Partition Status Register (register #26) (R) Table 6-9 Partition Status Register Bit Definition Bit(s) Name Description 26.15:8 Reserved Always 0. 26.7 PartP1 1 : Port 1 has been partitioned 0 : Port 1 has not been partitioned Status is updated every 40 ns. 26.6 PartP0 1 : Port 0 has been partitioned 0 : Port 0 has not been partitioned Status is updated every 40 ns. 26.5 Reserved Ignored when read 26.4 PartP4 1 : Port 4 has been partitioned 0 : Port 4 has not been partitioned Status is updated every 40 ns. 26.3 Reserved Ignored when read 26.2 PartP3 1 : Port 3 has been partitioned 0 : Port 3 has not been partitioned Status is updated every 40 ns. 26.1 PartP2 1 : Port 2 has been partitioned 0 : Port 2 has not been partitioned Status is updated every 40 ns. 26.0 Reserved Ignored when read
R/W R R
R
R R
R R
R
R
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MX98746
J. Elastic Buffer Over/Underflow Status Register (register #27) (R) Table 6-10 Elastic Buffer Over/Underflow Status Register Bit Definition Bit(s) Name Description 27.15:0 Reserved Always 0. 27.7 EBOUF1 1 : Elastic Buffer Over/Underflow at Port 1 0 : Normal Condition. Clear to 0 after read. 27.6 EBOUF0 1 : Elastic Buffer Over/Underflow at Port 0 0 : Normal Condition. Clear to 0 after read. 27.5 Reserved Ignored when read 27.4 EBOUF4 1 : Elastic Buffer Over/Underflow at Port 4 0 : Normal Condition. Clear to 0 after read. 27.3 Reserved Ignored when read 27.2 EBOUF3 1 : Elastic Buffer Over/Underflow at Port 3 0 : Normal Condition. Clear to 0 after read. 27.1 EBOUF2 1 : Elastic Buffer Over/Underflow at Port 2 0 : Normal Condition. Clear to 0 after read. 27.0 Reserved Ignored when read
R/W R R
R
R R
R R
R
R
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K. Jabber Status Register (register #28) (R) Table 6-11 Jabber Status Register Bit Definition Bit(s) Name Description 28.15:0 Reserved Always 0. 28.7 JABP1 1 : Receive Jabber Active at Port 1 0 : No Jabber condition at Port 1 28.6 JABP0 1 : Receive Jabber Active at Port 0 0 : No Jabber condition at Port 0 28.5 Reserved Ignored when read 28.4 JABP4 1 : Receive Jabber Active at Port 4 0 : No Jabber condition at Port 4 28.3 Reserved Ignored when read 28.2 JABP3 1 : Receive Jabber Active at Port 3 0 : No Jabber condition at Port 3 28.1 JABP2 1 : Receive Jabber Active at Port 2 0 : No Jabber condition at Port 2 28.0 Reserved Ignored when read
R/W R R R R R R R R R
L. Isolation Status Register (register #29) (R) Table 6-12 Isolation Status Register Bit Definition Bit(s) Name Description 29.15:0 Reserved Always 0. 29.7 ISO1 1 : Port Isolation is occuring at port 1, 0 : Port Isolation is not occuring at port 1. 29.6 ISO0 1 : Port Isolation is occuring at port 0, 0 : Port Isolation is not occuring at port 0. 29.5 Reserved Ignored when read 29.4 ISO4 1 : Port Isolation is occuring at port 4, 0 : Port Isolation is not occuring at port 4. 29.3 Reserved Ignored when read 29.2 ISO3 1 : Port Isolation is occuring at port 3, 0 : Port Isolation is not occuring at port 3. 29.1 ISO2 1 : Port Isolation is occuring at port 2, 0 : Port Isolation is not occuring at port 2. 29.0 Reserved Ignored when read R/W R R R R R R R R R
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MX98746
M. Configuration Register (register #31) (R/W) Table 6-13 Configuration Register Bit Definition Bit(s) Name Description 31.15 Reserved Reserved for further usage. 31.14 L40H80 1:Internal arbiter will qualify EDENL for more than 80 ns. 0:Internal arbiter will qualify EDENL for more than 40 ns. Power on low. 31.13:12 Reserved Reserved for further usage. 31.11 EECF Power on reset value of LDS0. After power on reset, Write 1 to this bit will not make EEPROM operation. When EECF is low, then value on corresponding pins (known as hardwire setting) will be latched by MX98746 and overwrite the default setting of MX98746. 31.10 Reserved Force to High all the time. 31.9 MONITOR 1 : Set XRC II to monitor mode and monitor serial output of internal state machine through LED7..0 0 : Put MX98746 in normal mode. 31.8 INTARB 0:Internal Arbitor function is disabled. 1:Internal Arbitor function is enabled Power on low. 31.7 FLWSPEC 1 : Partition function meets IEEE 802.3u i.e. when two ports collide more than 128 times, two ports will be partitoned by MX98746 simultaneously. 0 : Those ports which Receive after Transmit will be partitioned. (Same as MX98741) i.e. ports encounter transmit collision will be paritioned only. Value on LED0 will be stored in this bit in case EECONF is 0. 31.6 Reserved Reserved for further usage 31.5 Reserved Reserved for further usage 31.4:0 PHY[4:0] Physical address of MX98746. When EECONF is set to 0 (Disabled), value on LED[7:3] will be stored in these five bits at the rising edge of RESETL. If EECONF is set to high, value from EEPROM will overwrite the hardwire setting.
R/W R/W
R/W
R R/W
R
R/W
R/W
R/W
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MX98746
6.4 EEPROM Mapping Word # 5 4 3 2 1 0 Bit 15 .................. 8 MSB of Register #31 MSB of Register #20 MSB of Register #19 MSB of Register #18 MSB of Register #17 MSB of Register #16 7 .......................... 0 LSB of Register #31 LSB of Register #20 LSB of Register #19 LSB of Register #18 LSB of Register #17 LSB of Register #16
7.0 ABSOLUTE MAXIMUM RATINGS
Table 7-1 Absolute Maximum Rating for MX98746
RATING Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (TSTG) Operating Temperature Range Power Dissipation (PD) VALUE 4.75V to 5.25V -0.5V to VCC+0.5V -0.5V to VCC+0.5V -55 to 150 C C 0 to 70 C C 750 mW
ESD rating (Rzap=1.5K, Czap=100pF) 2000V
Notice : Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cauase permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
8.0 DC Characteristics
Table 8-1 DC Characteristics for MX98746 SYMBOL PARAMETER A. Supply Current ICC Average Active (TXing/RXing) Supply Current ICCIDLE Average Idle Supply Current CONDITIONS X1 = 25MHz VIN = Switching X1 = 25MHz VIN=VCC/GND X1=Undriven GND = 0V VI=VCC/GND Ioh = -2mA/-4mA /-8mA Iol = 2mA/ 4mA /8mA VOUT=VCC/GND Ioh = -20uA Iol = 20uA MIN. MAX. UNIT
2.0 -1.0 2.4 -10.0
150 10 600 0.8 VCC+0.5 1.0 0.4 10.0
mA mA uA V V uA V V uA V V V V
IDD Static IDD Current B. TTL Inputs, Outputs, Tri-States Vil Maximum Low Level Input Voltage Vih Minimum High Level Input Voltage Iin Input Current Voh Minimum High Level Output Voltage (Others/MII/Expansion) Vol Maximum Low Level Output Voltage (Others/MII/Expansion) Ioz Maximum TRI-STATE Output Leakage Current C. CMOS Inputs, Outputs Voh Minimum High Level Output Voltage Vol Maximum Low Level Output Voltage Vil Maximum Low Level Input Voltage Vih Minimum High Level Input Voltage Iin Input Current
VCC-0.1 0.1 0.8 2.0 -
VI=VCC/GND
-1.0
1.0
uA
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MX98746
9.0 AC CHARACTERISTICS AND WAVEFORMS
A. Media Independent Interface
T01 T02 T03
MDC T04 MDIO T05
Figure 9-1 MDIO Timing Relationship MDC
Symbol T01 T02 T03 T04 T05a T05b
Description Period for MDC High Time for MDC Low Time for MDC MDIO Setup to MDC rising edge (sourced by STA) MDIO Hold to MDC rising edge (sourced by STA) MDIO Hold to MDC rising edge (source by XRC)
MIN. 400 160 160 10 10 18
MAX. 25
UNIT ns ns ns ns ns ns
B. Data Transceiver Interface
LSCLK T31 TDAT[4:0]
Figure 9-2 Transmit Signal Timing Relationships at the DT
Symbol T31
Description TDAT[4:0] to LSCLK Delay Time
MIN. 10
MAX. 15
UNIT ns
Note : Tested under 30pF loading.
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MX98746
T41 T42 T43
RXCLK T44 RDAT[4:0] T45
Figure 9-3 Receive Signal Timing Relationships at the DT
Symbol T41 T42 T43 T44 T45
Description RSCLK Period (Note 1) RSCLK Pulse Width High RSCLK Pulse Width Low Time RDAT[4:0] Valid to RSCLK Rise RSCLK Rise to RDAT[4:0] Invalid
MIN. 40 11 20 2 4
MAX. 40 -
UNIT ns ns ns ns ns
Note 1 : The accurate RSCLK frequency shall be 25 MHz +/- 50 ppm.
RESETL
T51
Figure 9-4 Timing Constraint RESEL
Symbol T51
Description Pulse Width for RESETL
MIN. 800
MAX. -
UNIT us
Note : RESETL must keep active low until LSCLK is stable more than 200 us.
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MX98746
C. Expansion Port Interface
LSCLK
ANYACT
T71
EDENL
T72
T73
EDACT
Figure 9-7 Expansion Port with One port activates
Symbol T71 T72 T73
Description ANYACT asserted to EDENL asserted (Note 3) LSCLK rising to EDACT asserted (Note 1, 2) LSCLK rising to EDACT deassert
MIN.
MAX. 80 20 20
UNIT ns ns ns
Note 1 : EDENL will be filtered by 2 LSCLK clock within MX98746. Whenever MX98746 detects EDENL, it will assert EDACT at the rising edge of LSCLK Note 2 : Expansion port data will be released onto EDAT[4:0] at the next LSCLK rising edge right after EDACT is asserted which is not shown in this figure. Note 3 : ANYACT has not any timing relationship to LSCLK in MX98746. i.e. it is asynchronous to LSCLK.
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MX98746
LSCLK
ANYACT1
ANYACT2
EDENL1
T81
EDENL2
EDACT1
T82
JAMI T83 JAMO1
Figure 9-8 Expansion Port with Collision (Note 1)
Symbol T81 T82 T83
Description Valid EDENL duration to make EDACT active Collision Condition to JAMI asserted (Note 2) JAMO asserted to JAMI asserted (Note 3)
MIN. 80
MAX. 10 10
UNIT ns ns ns
Note 1 : EDENL2 asserted after collision will not make EDACT2 assert in MX98746 due to MX98746 will mask activity from expansion port from cessation of collision to cessation of ANYACT2. Note 2 : Deassert timing is the same Note 3 : Deassert timing is the same. Either T72 or T73 should cause JAMI assert Note 4 : EDENL, JAMI and EDCRS (not shown in this timing) should be filtered by LSCLK to resolve asynchronous issue.
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MX98746
EPCLK T91 EDAT /I/ /J/ /K/ /D1/ T92 /T/ T93 /R/
Figure 9-9 EPCLK and EDAT Timing Relationship
Symbol T91 T92 T93
Description EPCLK to EDAT delay time (EPCLK and EDAT outputed from MX98746) EDAT Setup Time (Input to MX98746) EDAT Hold Time (Input to MX98746)
MIN. 12 5 5
MAX. 16 -
UNIT ns ns ns
D. LED Display
T96
LEDEN T97 LDS2_0 T99 LED7_0 T100 T98
Figure 9-10 Timing Relationship for LED Display
Symbol T96 T97 T98 T99 T100
Description LEDEN Period LDS2_0 Setup Time LDS2_0 Hold Time LED7_0 Setup Time LED7_0 Hold Time
MIN. 9.9 4.0 4.9 4.0 4.9
MAX. 10.1 -
UNIT ms ms ms ms ms
Note : Where LED7_0 definition relative to LDS2_0 configuration, please reference pin description of LDS2_0
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MX98746
11.0 PACKAGE INFORMATION
128-PIN PLASTIC QUAD FLAT PACK
ITEM a b c d e L1 L ZE E3 E ZD D3 D A1 A Note
NOTE:
MILLIMETERS 14.00 .05 .20 [Typ.] 20.00 .05 1.346 .50 [Typ.] 1.60 .1 .80 .1 .75 [Typ.] 12.50 [Typ.] 17.20 .2 .75 [Typ.] 18.50 [Typ.] 23.20 .2 .25 .1 min. 3.40 .1 max. Short Lead
INCHES 5.512 .02 .08 [Typ.] 7.87 .002 .530 .20 [Typ.] 0.63 .04 .31 .04 .30 [Typ.] 4.92 [Typ.] 6.77 .08 .30 [Typ.] 7.28 [Typ.] 9.13 .08 .10 .04 min. 1.34 .04 max. Short Lead
A 128 1 102 103 ZD
D c D3
65
64
E3
a
E
39 38 ZE
H
I L1 d A1
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
b
e L
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MX98746
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309 FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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